1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit capable of suppressing effectively occurrence of soft-errors that might otherwise occur frequently.
2. Description of Related Art
Along with the progress of the semiconductor techniques for miniaturizing elements and lowering their operation voltages, there have appeared semiconductor integrated circuits having been improved more in integration. As a result, the functions and performances of those improved semiconductor integrated circuits have also been enhanced, thereby the number of logic circuits integrated in those circuits is increasing.
In case of a semiconductor integrated circuit including many logic circuits, soft-errors caused by radiation have now come to arise not only in memory cells, but also in logic circuits. This problem is closed up recently. For example, such soft-errors that arise in logic circuits are inversion errors and SET (Single Event Transient) errors. An inversion error occurs, for example, in a circuit that holds information temporarily (information holding circuit) such as a flip-flop (F/F) circuit, a latch circuit, a register circuit, so that the held information is inverted. A SET error occurs as follows. When neutron rays are injected into a transistor of a logic gate of an LSI to generate charge, the operation characteristics of the logic gate are changed in a transient state. Then, the change is transmitted into the LSI, thereby the LSI comes to malfunction.
There is a well-known technique capable of suppressing occurrence of such soft-errors by improving the object circuit configuration. For example, in order to avoid inversion errors, one of such well-known techniques prevents soft-errors by adding a circuit capable of preventing information inversion in the information holding circuit (transistors and capacitance elements are added) to the object LSI. On the other hand, there are well-known techniques related to coincidence circuits and majority-decision circuits, which can be employed to prevent SET errors.
There is also another well-known technique capable of suppressing occurrence of soft-errors by employing inventive layouts and manufacturing processes of such transistors as the MISFET (Metal-Insulator-Semiconductor Field Effect Transistor). For example, one of such well-known methods prevents invasion of charge generated by radiation into the drain (node) diffusion layer of the object MISFET (to reduce the amount of charge to be collected into the layer) (e.g., patent document 1 and non-patent document 1). There is still another well-known method that adjusts the impurity profile in the object substrate to prevent occurrence of soft-errors by employing inventive manufacturing processes.
The patent document 1 (Japanese Patent Application Laid Open No. 2002-353413) discloses a technique that provides a diffusion layer for collecting charge near the object MISFET of a memory cell. According to the technique disclosed in the patent document 1, the diffusion layer has the same conductivity type as that of the diffusion layer of the MISFET of an SRAM cell or F/F circuit and this newly provided diffusion layer suppresses the invasion of charge into the cell node.
The non-patent document 1 discloses a technique related to a relationship between collection of charge generated by radiation into a target diffusion layer (e.g., memory node diffusion layer) and the distance between an adjacent diffusion layer and the target diffusion layer. This non-patent document 1 describes that the longer the distance from the adjacent diffusion layer is, the more the amount of collected charge is reduced (the effective funneling length is reduced).
[Non-patent document 1] Eiji Takeda, et al., “A Cross Section of α-Particle-Induced Soft-Error Phenomena in VLSI's” IEEE TRANSACTION ON ELECTRON DEVICES, VOL. 36, NO. 11, pp. 2567-2575, 1989